1. Field of the Invention
The present invention relates to a method of manufacturing a photoelectric conversion device.
2. Description of the Related Art
For conventional semiconductor devices, CMP (Chemical Mechanical Polishing) is widely used in a step of forming conductive lines with a damascene structure. In the CMP, polishing is generally done using an abrasive called slurry. The polishing rate of a metal conductive line is higher than that of an insulating film. The difference in the polishing rate sometimes degrades the planarity of the polished surfaces (the upper surfaces of the metal conductive line and insulating film). More specifically, in the polishing step using CMP, polishing progresses faster in a region where the pattern density of metal conductive lines is locally high than in a region where the pattern density of metal conductive lines is low. This may cause planarity degradation called erosion. A measure for preventing this is widely used, in which polishing by CMP is performed after forming, in the low pattern density region, dummy conductive lines that are not used for electrical connections.
However, if the dummy conductive lines remain even after the polishing, conductive lines need to be laid out while being kept off the dummy conductive lines, which do not aim at electrical connections. This may limit the degree of freedom of conductive line layout. In addition, the capacitance between the conductive lines may increase due to the existence of the dummy conductive lines, resulting in delay in the conductive lines. In a solid-state image capturing element, dummy conductive lines remaining above the photoelectric converter shield light that should strike the photoelectric converter, and lower the sensitivity of the photoelectric converter. Japanese Patent Laid-Open No. 2004-071790 proposes removing dummy conductive lines after polishing of CMP. More specifically, a concave portion 128 is formed by etching an uppermost interlayer insulating film 127 of an image capturing element portion 129 so as to expose a dummy conductive line 126A. Then, the dummy conductive line 126A is removed by etching. Japanese Patent Laid-Open No. 2004-071790 also describes that the bottom surface of the concave portion may further be planarized by etching, a filler may be injected into the concave portion to make that portion flush with a peripheral circuit portion 130, and planarization may then be done all over the structure. In this manufacturing method, the process of improving the planarity of the upper surface of the uppermost interlayer insulating film 127 is complex as a whole.